The present disclosure herein relates to semiconductor memory devices, and more particularly, to nonvolatile memory devices and methods of operating thereof.
In general, semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices. The volatile semiconductor memory device has a fast read or write speed but loses its stored contents when external power supply is cut off. On the contrary, the nonvolatile semiconductor memory device retains its stored contents even if external power supply is cut off. Therefore, the nonvolatile semiconductor memory device may be used to memorize the contents that need to be stored regardless of power supply. The nonvolatile semiconductor memory device may include a mask read-only memory (MROM), a Programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Generally, MROM, PROM, and EPROM may have difficulties performing erase and write operations without additional devices and thus general users may have difficulties updating their memory contents. On the contrary, EEPROM is capable of electrically performing ease and write operations and thus becomes extensively applied to system programming or an auxiliary memory device, which requires continuous update. A flash EEPROM (hereinafter, referred to as a flash memory) has a higher degree of integration than a typical EEPROM and thus may be advantageous to an application requiring a high capacity auxiliary memory device. Among flash memories, a NAND type flash EEPROM (hereinafter, referred to as a NAND-type flash memory) has a higher degree of integration than other flash memories.
A flash memory device based on the above-mentioned EEPROM technology may store a large amount of information. Then, the flash memory device may read stored information at any time. Due to a demand for a high capacity of a flash memory device, the degree of integration in memory cells has been increased. Moreover, many efforts are being made to store multi-bit data in one memory cell in order to achieve high capacity.
Furthermore, due to the high capacity, interference between memory cells may increasingly affect performance of the memory cells. Reliability of data is affected by interference between memory cells and dummy cells and between bit lines and dummy bit lines.